Semiconductor element integration techniques have shifted from two-dimensional integration techniques to three-dimensional integration techniques so as to provide for high degrees of integration of semiconductor devices. This causes semiconductor integrated circuit devices having a three-dimensional multilayer structure to receive attention. A chip-on-wafer process (COW process) (e.g., Patent Literature (PTL 1)) is known as a process for producing a three-dimensional integrated semiconductor circuit device. In the COW process, a second semiconductor wafer is diced to give chips, and the chips are stacked on a first semiconductor wafer. Assume that through holes (through-silicon vias; TSVs) are prepared in the COW process. In this case, the vias are prepared by performing etching using a photoresist.